In theory, digital sample rate conversion between two different clock rates can be performed without introduction of sample error (phase noise) if the two sample frequencies are related by a rational ratio. This is typically accomplished by interpolating to the lowest frequency that is a multiple of both the source and sink sample rates, and then decimating to the required sink sample rate. If the two sample rates are not rationally related, as will be the case at least part of the time if they are varying with respect to one another, then phase noise will be introduced even if the source and sink sample clocks are ideal. In practice, jitter on the source and sink clocks result in the introduction of phase noise even if the rates are related rationally, so noise-shaped delta-sigma modulated fractional-N (“Frac-N”) sample rate converters are often the best choice even when the source and sink clocks are rationally related.
Fractional rate interpolators create an effective interpolation rate that is the average of a series of integer hold values. For example, a fractional interpolation rate of 7.5 could be created by alternating 7 cycle sample-holds with 8 cycle sample-holds. Sequence repetition such as this would, however, create significant tones in the spectral response of the interpolator. If instead a random sequence of 7's and 8's was chosen, with an equal number of 7's and 8's on average, then the same fractional interpolation rate would be achieved, but the quantization error would appear as noise spread across the spectrum instead of the more discrete tones produced by the alternating scheme previously described.
Delta-sigma modulated fractional-N interpolators operate on this principle, except that rather than generate a random stream of 7's and 8's (in the context of the foregoing example), the stream is generated to shape the quantization noise spectrally such that it is reduced in the frequencies of interest, and appears at frequencies that are easily filtered. The principles of delta-sigma modulation are well known in the signal processing arts and are described in, e.g., “Delta-Sigma Data Converters—Theory, Design and Simulation”, Norsworthy, et al., IEEE Press, 1997.
Both Integer and Fractional-N digital sample rate converters have been described in the literature; see U.S. Pat. No. 5,497,152 issued Mar. 5, 1996 and entitled “Digital-to-Digital Conversion Using Non-Uniform Sample Rates” which is incorporated herein by reference in its entirety; and “Sample-Rate Conversion: Algorithms and VLSI Implementation”, Diss. ETH No. 10980, Swiss Federal Institute of Technology, Zurich (1995), also incorporated herein by reference in its entirety. Many issues associated with tracking source and sink clocks have also been addressed in the prior art.
The above-referenced solutions, however, have several drawbacks. Most notably, each requires a complete digital phase lock loop (PLL) in addition to the interpolator in order to provide the desired tracking between source and sink clock domains. This PLL arrangement is costly in terms of additional complexity and power consumption. It also reduces the robustness of the interpolator device as a whole. What would be ideal is a solution where the PLL could be obviated in favor of a simpler and less power-consumptive architecture.
Additionally, prior art solutions do not provide the ability to dynamically adapt the operation of the interpolator (or decimator) as a function of operational conditions or parameters, such as transmitter power. Such prior art interpolators also generate significant phase noise which may undesirably fall within certain bands of interest, thereby degrading the performance of the parent device (e.g., RF transmitter).